Dc and ac magnetic field protection for mram device using magnetic-field-shielding structure

ABSTRACT

In some embodiments, the present application provides an integrated chip. The integrated chip includes a chip comprising a semiconductor device. A shielding structure abuts the chip. The shielding structure comprises a first horizontal region adjacent to a first horizontal surface of the chip. The first horizontal region comprises a first multilayer structure comprising a first dielectric layer and two or more metal layers. The first dielectric layer is disposed between the two or more metal layers.

REFERENCE TO RELATED APPLICATIONS

This application is a Continuation of U.S. application Ser. No. 17/393,651, filed on Aug. 4, 2021, which is a Divisional of U.S. application Ser. No. 16/381,410, filed on Apr. 11, 2019 (now U.S. Pat. No. 11,088,083, issued on Aug. 10, 2021), which claims the benefit of U.S. Provisional Application No. 62/692,238, filed on Jun. 29, 2018. The contents of the above-referenced patent applications are hereby incorporated by reference in their entirety.

BACKGROUND

Many modern day electronic devices contain electronic memory, such as hard disk drives or random access memory (RAM). Electronic memory may be volatile memory or non-volatile memory. Non-volatile memory is able to retain its stored data in the absence of power, whereas volatile memory loses its data memory contents when power is lost. Magnetic tunnel junctions (MTJs) can be used in hard disk drives and/or magnetic RAM (MRAM), and thus are promising candidates for next generation memory solutions.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIGS. 1A, 1B, 1C illustrate perspective views of some embodiments of a memory device that comprises a chip and makes use of a magnetic field shielding structure in accordance with some embodiments, with the front portions removed to more clearly depict inner portions of the memory device, and FIG. 1D illustrates a perspective view of the chip of FIGS. 1A, 1B, 1C, with the front portions removed to more clearly depict inner portions of the chip.

FIG. 1E illustrates a perspective view of some embodiments of a packaged memory device that comprises a chip and makes use of a magnetic field shielding structure in accordance with some embodiments, with the front portions removed to more clearly depict inner portions of the packaged memory device.

FIGS. 2A-2C depict top views of FIGS. 1A-1C, respectively, including a memory device that makes use of a magnetic-field-shielding structure in accordance with some embodiments.

FIGS. 2D-2F depict top views of some embodiments of FIGS. 1A-1C, respectively, including a memory device that makes use of a magnetic-field-shielding structure in accordance with some embodiments.

FIGS. 3A-3C depict cross-sectional views of some embodiments of FIGS. 2D-2F, respectively, including a memory device that makes use of a magnetic-field-shielding structure in accordance with some embodiments.

FIGS. 4A-4C depict cross-sectional views of some embodiments of FIGS. 2D-2F, respectively, including a memory device that makes use of a magnetic-field-shielding structure in accordance with some embodiments.

FIGS. 5A-5C and 6A-6C depict cross-sectional views of some embodiments of FIGS. 3A-3C and 4A-4C, respectively, including a memory device that makes use of a magnetic-field-shielding structure in accordance with some embodiments.

FIGS. 7A-7C and 8A-8C depict cross-sectional views of some embodiments of FIGS. 3A-3C and 4A-4C, respectively, including a memory device that makes use of a magnetic-field-shielding structure in accordance with some embodiments.

FIGS. 9A-9C and 10A-10C depict cross-sectional views of some embodiments of FIGS. 3A-3C and 4A-4C, respectively, including a memory device that makes use of a magnetic-field-shielding structure in accordance with some embodiments.

FIGS. 11A-11C and 12A-12C depict cross-sectional views of some embodiments of FIGS. 3A-3C and 4A-4C, respectively, including a memory device that makes use of a magnetic-field-shielding structure in accordance with some embodiments.

FIGS. 13A-13C and 14A-14C depict cross-sectional views of some embodiments of FIGS. 3A-3C and 4A-4C, respectively, including a memory device that makes use of a magnetic-field-shielding structure in accordance with some embodiments.

FIGS. 15A-15C and 16A-16C depict cross-sectional views of some embodiments of FIGS. 3A-3C and 4A-4C, respectively, including a memory device that makes use of a magnetic-field-shielding structure in accordance with some embodiments.

FIGS. 17A-17C and 18A-18C depict cross-sectional views of some embodiments of FIGS. 3A-3C and 4A-4C, respectively, including a memory device that makes use of a magnetic-field-shielding structure in accordance with some embodiments.

FIGS. 19A-19C and 20A-20C depict cross-sectional views of some embodiments of FIGS. 3A-3C and 4A-4C, respectively, including a memory device that makes use of a magnetic-field-shielding structure in accordance with some embodiments.

FIGS. 21A-21C and 22A-22C depict cross-sectional views of some embodiments of FIGS. 3A-3C and 4A-4C, respectively, including a memory device that makes use of a magnetic-field-shielding structure in accordance with some embodiments.

FIGS. 23A-23C and 24A-24C depict cross-sectional views of some embodiments of FIGS. 3A-3C and 4A-4C, respectively, including a memory device that makes use of a magnetic-field-shielding structure in accordance with some embodiments.

FIGS. 25A-25C and 26A-26C depict cross-sectional views of some embodiments of FIGS. 3A-3C and 4A-4C, respectively, including a memory device that makes use of a magnetic field shielding structure in accordance with some embodiments.

FIGS. 27, 28A, 28B, 29, 30A, 30B, 31, 32A, and 32B illustrate perspective views of various embodiments of a method for forming sections of a magnetic field shielding structure.

FIGS. 33, 34, 35A-35C, and 36A-36C illustrate cross-sectional views of various embodiments of a method for forming a magnetic field shielding structure around a chip.

FIG. 37 illustrates a block diagram of some embodiments of the method of FIGS. 27, 28A, 28B, 29, 30A, 30B, 31, 32A, and 32B.

FIG. 38 illustrates a block diagram of some embodiments of the method of FIGS. 33, 34, 35A-35C, and 36A-36C.

DETAILED DESCRIPTION

The present disclosure provides many different embodiments, or examples, for implementing different features of this disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

A magnetic tunnel junction (MTJ) includes first and second ferromagnetic films separated by a tunnel barrier layer. One of the ferromagnetic films (often referred to as a “reference layer”) has a fixed magnetization direction, while the other ferromagnetic film (often referred to as a “free layer”) has a variable magnetization direction. For MTJs with positive tunnelling magnetoresistance (TMR), if the magnetization directions of the reference layer and free layer are in a parallel orientation, it is more likely that electrons will tunnel through the tunnel barrier layer, such that the MTJ is in a low-resistance state. Conversely, if the magnetization directions of the reference layer and free layer are in an anti-parallel orientation, it is less likely that electrons will tunnel through the tunnel barrier layer, such that the MTJ is in a high-resistance state. Consequently, the MTJ can be switched between two states of electrical resistance, a first state with a low resistance (Rp: magnetization directions of reference layer and free layer are parallel) and a second state with a high resistance (RAP: magnetization directions of reference layer and free layer are anti-parallel). It is noted that MTJs can also have a negative TMR, e.g., lower resistance for anti-parallel orientation and higher resistance for parallel orientation.

Because of their binary nature, MTJs are used in memory cells to store digital data, with the low resistance state Rp corresponding to a first data state (e.g., logical “0”), and the high-resistance state RAP corresponding to a second data state (e.g., logical “1”). Thus, some chips include arrays of MRAM cells where each MRAM cell makes use of an MTJ to store a data state. However, when such a chip comes under the presence of an external magnetic field, the external magnetic field can undesirably “flip” the data states stored in the MRAM cells, leading to data retention problems. To mitigate the adverse effects of external magnetic fields, the present disclosure contemplates at least partially surrounding an MRAM chip with a magnetic-field-shielding structure. The magnetic-field-shielding structure at least partially surrounds the chip and defines a magnetically-shielded zone surrounding the chip. The magnetically-shielded zone has a first magnetic field magnitude that is less than a second magnetic field magnitude immediately outside of an outermost surface of the magnetic-field-shielding structure. Thus, the magnetic-field-shielding structure reduces the magnetic field experienced by the chip, thereby improving data retention within the MRAM cells of the chip.

FIG. 1A illustrates a perspective view of a memory device 100 a in accordance with some embodiments with the front portions removed to more clearly depict inner portions of the memory device. The memory device 100 a includes a chip 106 and a magnetic field shielding structure 105. Often, the chip 106 includes transistors disposed in a semiconductor substrate, and an array of MRAM cells arranged in an interconnect structure over the semiconductor substrate. An innermost surface of the magnetic field shielding structure 105 at least partially surrounds the chip 106 and establishes a magnetically-shielded-zone proximate to the chip 106. Because of the magnetic field shielding structure 105, the magnetically-shielded zone has a first magnetic field magnitude that is less than a second magnetic field magnitude immediately outside of an outermost surface of the magnetic field shielding structure 105. Thus, the magnetic field shielding structure 105 reduces the magnetic field experienced by the chip 106, thereby helping to improve data retention within MRAM cells on the chip 106. In some embodiments, the first magnetic field magnitude is at least 80 percent less than the second magnetic field magnitude immediately outside the outermost surface of the magnetic field shielding structure 105. In yet another embodiment, the first magnetic field magnitude is 316 oersted (Oe) and the second magnetic field magnitude is 2015 Oe immediately outside the outermost surface of the magnetic field shielding structure 105. The magnetic field shielding structure protects the chip 106 from both direct current (DC) and alternating current (AC) magnetic fields.

Above an upper surface of the chip 106, a top region 122 of the magnetic field shielding structure 105 comprises a first instantiation of a first multilayer stack 103 a. Below a lower surface of the chip 106, a bottom region 126 of the magnetic field shielding structure 105 comprises a second instantiation of the first multilayer stack 103 a such that individual layers of the second instantiation are arranged in parallel with individual layers of the first instantiation. A sidewall region 124 defined between the top region 122 of the magnetic field shielding structure 105 and the bottom region 126 of the magnetic field shielding structure 105 comprises a third instantiation of the first multilayer stack 103 a. The individual layers of the third instantiation of the first multilayer stack 103 are rotated 90 degrees relative to the individual layers of the first and second instantiations. The sidewall region 124 is laterally separated from sidewalls of the chip 106.

For each instantiation, the first multilayer stack 103 a comprises one or more magnetic layers 102 and one or more dielectric layers 104. A bottom most layer of the first multilayer stack 103 a comprises the magnetic layer 102 and a top most layer of the first multilayer stack 103 a comprises the magnetic layer 102. In some embodiments, the magnetic layer 102 and the dielectric layer 104 are individually coated with an insulating adhesive material. In some embodiments, an insulating adhesive layer is placed between each magnetic layer 102 and dielectric layer 104 in the first multilayer stack 103 a. The insulating adhesive layer defines a top surface and a bottom surface of the first multilayer stack 103 a. Thus, in some embodiments, the first instantiation, the second instantiation, and the third instantiation each have the same number of magnetic layers and dielectric layers as one another, with those respective layers being arranged in the same order, having the same respective compositions, and having the same respective thicknesses for the first, second, and third instantiations. For example, in some embodiments, the first multilayer stack can include 3 magnetic layers and 2 dielectric layers that alternate with one another. In yet another embodiments, the first multilayer stack can include approximately 3 to 100 magnetic layers and approximately 2 to 99 dielectric layers that alternate with one another.

In some embodiments, the first multilayer stack 103 a comprises one or more insulating adhesive layers respectively overlaying the one or more magnetic layers 102 and the one or more dielectric layers 104 that respectively overlay the one or more magnetic layers 102. The magnetic layer 102 is a sheet of continuous magnetic material having a length and width which are greater than a length and a width, respectively, of the upper surface of the chip 106. The dielectric layer 104 is a sheet of continuous dielectric material arranged over the magnetic layer 102. The dielectric layer 104 has a length and width which are greater than the length and width, respectively, of the upper surface of the chip 106.

Electric connectors 108 extend through openings in the magnetic field shielding structure 105 and couple to the chip 106, specifically through the third instantiation of the first multilayer stack 103 a located in the sidewall region 124. The electric connectors 108 extend through an opening on a face of the magnetic field shielding structure 105. The magnetic field shielding structure 105 is not electrically coupled to the electric connectors 108.

During operation of the chip 106, read and write operations are carried out on the array of MRAM cells. The presence of the magnetic field shielding structure 105 ensures that power used during write operations on the array of MRAM cells is not lost due to external influence. Instead, the magnetic field shielding structure 105 ensures power used during a write operation is contained within the chip 106. Additionally, any magnetic fields independent of the chip 106 will be redirected away from an area immediately outside an outer surface of the chip 106, thereby preventing any undesired change in a set or stored data state and increasing data retention of the array of MRAM cells in the chip 106.

Referring to FIG. 1B, a perspective view 100 b of some alternative embodiments of the memory device of FIG. 1A is provided in which the top region 122 of the magnetic shielding structure 105 comprises a first instantiation of a second multilayer stack 103 b. The bottom region 126 of the magnetic field shielding structure 105 comprises a second instantiation of the second multilayer stack 103 b. The sidewall region 124 defined between the top region 122 of the magnetic field shielding structure 105 and the bottom region 126 of the magnetic field shielding structure 105 comprises the magnetic layer 102. In some embodiments, the magnetic layer 102 within the sidewall region 124 is at least partially surrounded by an insulating adhesive layer and/or at least partially coated in the insulating adhesive material, but in the illustrated embodiment the magnetic layer 102 is a single continuous layer that has a thickness that is greater than or equal to a thickness of the magnetic layer 102 in the second multilayer stack 103 b. Electric connectors 108 extend through openings in the magnetic field shielding structure 105 and couple to the chip 106, specifically through the magnetic layer 102 within the sidewall region 124.

In each instantiation, the second multilayer stack 103 b comprises a plurality of strips of the magnetic layer 102 and a plurality of strips of the dielectric layer 104 separating the plurality of strips of the magnetic layer 102. Each strip in the plurality of strips of the magnetic layer 102 has a length greater than the length of the upper surface of the chip 106 and a width that is less than the width of the upper surface of the chip 106. Each strip in the plurality of strips of the dielectric layer 104 has a length greater than the length of the upper surface of the chip 106 and a width that is less than the width of the upper surface of the chip 106. In some embodiments, an insulating adhesive strip is placed between each strip in the plurality of strips of the magnetic layer 102 and the dielectric layer 104 in the second multilayer stack 103 b, and insulating adhesive layers are respectively placed at a top and bottom surface of the multilayer stack 103 b. In some embodiments, the second multilayer stack 103 b comprises at least three strips of the magnetic layer 102 and at least three strips of the dielectric layer 104. The top surface of the multilayer stack 103 b has a length and width that is greater than the length and width, respectively, of the upper surface of the chip 106.

Referring to FIG. 1C, a perspective view 100 c of some alternative embodiments of the memory device of FIG. 1A is provided in which the top region 122 of the magnetic shielding structure 105 comprises a first instantiation of a third multilayer stack 103 c. The bottom region 126 of the magnetic field shielding structure 105 comprises a second instantiation of the third multilayer stack 103 c. The sidewall region 124 defined between the top region 122 of the magnetic field shielding structure 105 and the bottom region 126 of the magnetic field shielding structure 105 comprises the magnetic layer 102. In some embodiments, the magnetic layer 102 within the sidewall region 124 is at least partially surrounded by an insulating adhesive layer and/or at least partially coated in the insulating adhesive material, but in the illustrated embodiment the magnetic layer 102 is a single continuous layer that has a thickness that is greater than or equal to a thickness of the magnetic layer 102 in the third multilayer stack 103 c. Electric connectors 108 extend through openings in the magnetic field shielding structure 105 and couple to the chip 106, specifically through the magnetic layer 102 within the sidewall region 124.

The third multilayer stack 103 c comprises a plurality of rectangles of the magnetic layer 102 and a grid of the dielectric layer 104 separating the plurality of rectangles of the magnetic layer 102. The plurality of rectangles of the magnetic layer 102 are spaced apart from one another in a series of rows and columns. The grid of the dielectric layer 104 comprises a plurality of linear segments of the dielectric layer 104 which perpendicularly intersect one another. The plurality of rectangles of the magnetic layer 102 are arranged in the grid of the dielectric layer 104 such that neighboring rectangles are separated from one another by at least one linear segment of the grid of the dielectric layer 104. In some embodiments, an insulating adhesive strip is placed between each rectangle in the plurality of rectangles of the magnetic layer 102 and each section of the grid of the dielectric layer 104, and insulating adhesive layers are respectively placed at a top and bottom surface of the third multilayer stack 103 c. In some embodiments, the third multilayer stack 103 c comprises at least nine rectangles of the magnetic layer 102 and at least six linear segments of the dielectric layer 104. The grid of the dielectric layer 104 has a length and width which are greater than the length and width, respectively, of the upper surface of the chip 106.

The magnetic layer 102 may be or comprise, for example, iron (Fe), cobalt (Co), nickel (Ni), some other magnetic material, some other conductive material, or the like. In some embodiments, the magnetic layer 102 may be formed to a thickness of approximately 10 micrometers to 1,000 micrometers, approximately 10 micrometers to 500 micrometers, approximately 500 micrometers to 1,000 micrometers, or some other suitable value. The dielectric layer 104 may be or comprise, for example, a non-magnetic material, a low κ dielectric, silicon oxide, a high κ dielectric, some other dielectric, or any combination of the foregoing. In some embodiments, the dielectric layer 104 may be formed to a thickness of approximately 10 nanometers to 1,000 micrometers, approximately 10 nanometers to 500 micrometers, approximately 500 micrometers to 1,000 micrometers, or some other suitable value. The electric connectors 108 may be or comprise, for example, copper, aluminum copper, aluminum, tungsten, some other conductive material, or the like. In some embodiments, the magnetic layer 102 comprises a magnetic material and the dielectric layer 104 comprises a non-magnetic material.

Referring to FIG. 1D, a perspective view 100 d of some alternative embodiments of the chip 106 of FIG. 1A is provided in which the chip 106 includes a semiconductor substrate 109 and an interconnect structure 111 disposed over the semiconductor substrate 109. Often, the chip includes transistors 110 disposed in the semiconductor substrate 109, and an array of MRAM cells (e.g., MRAM cell 112) arranged in the interconnect structure 111. In some embodiments, the chip 106 has a first face on which active devices, such as transistors 110 and an array of MRAM cells, are disposed, and a second face adjacent the first face, the second face defines an upper surface of the chip 106.

Referring to FIG. 1E, a perspective view 100 e of some alternative embodiments of the memory device of FIG. 1A is provided in which the chip 106 and the magnetic field shielding structure 105 are enveloped by an insulating structure 120, such as a molding compound, epoxy, resin, ceramic material, or combinations thereof, defining a package structure 121. The insulating structure 120 at least partially fills a space between an outer surface of the chip 106 and an inner surface of the magnetic field shielding structure 105. The insulating structure 120 at least partially surrounds an outer surface of the magnetic field shielding structure 105. The electric connectors 108 extend through the insulating structure 120 and the magnetic field shielding structure 105 to couple to the chip 106. The electric connectors 108 respectively comprise a conductive contact lead 108 a and a conductive wire 108 b. In some embodiments, the conductive contact lead 108 a extends through the magnetic field shielding structure 105. In yet another embodiment, the conductive contact lead 108 a does not extend through the magnetic field shielding structure 105. The conductive wire 108 b directly contacts the conductive contact lead 108 a and is electrically coupled to the chip 106. The package structure 121 is configured to be mounted on a printed circuit board (PCB) in which each conductive contact lead 108 a in the electric connectors 108 electrically couple to the PCB.

Referring to FIG. 2A, a top view 200 a of the memory device of FIG. 1A is provided in which the length L₂ and the width W₂ of the chip 106 are respectively less than the length L₁ and the width W₁ of an upper surface of the magnetic shielding structure 105. The length L₂ of the chip 106 is within a range of approximately 0.5 millimeters to approximately 20 millimeters, and the width W₂ of the chip 106 is within a range of approximately 0.5 millimeters to approximately 20 millimeters. The length L₁ of the upper surface of the magnetic shielding structure 105 is within a range of approximately 4 millimeters to approximately 10 centimeters, and the width W₁ of the upper surface of the magnetic shielding structure 105 is within a range of approximately 4 millimeters to approximately 10 centimeters, or some other suitable value, for example. In some embodiments, the electric connectors 108 vary in size.

Referring to FIG. 2B, a top view 200 b of the memory device of FIG. 1B is provided in which a width of a strip in the plurality of strips of the magnetic layer 102 is within a range of approximately 10 micrometers to approximately 1,000 micrometers, or some other suitable value. A width of a strip in the plurality of strips of the dielectric layer 104 is within a range of approximately 10 nanometers to approximately 1,000 micrometers, or some other suitable value.

Referring to FIG. 2C, a top view 200 c of the memory device of FIG. 1C is provided in which a width of a rectangle in the plurality of rectangles of the magnetic layer 102 is within a range of approximately 10 micrometers to approximately 1,000 micrometers, or some other suitable value. A width of a linear segment in the plurality of linear segments of the grid of the dielectric layer 104 is within a range of approximately 10 nanometers to 1,000 micrometers, or some other suitable value.

With reference to a range of values used for the length L₂ and the width W₂ of the chip 106 and the length L₁ and the width W₁ of an upper surface of the magnetic shielding structure 105 described in relation to FIG. 2A above, it is to be understood that the range of values may be used with embodiments of the memory device in any one of the FIGS. 2B and 2C and their respective perspective view FIGS. 1B and 1C. With reference to FIGS. 2A-2C, a vertical line P_(x) along the x-axis represents a location in which cross-sectional views in the z-x plane are taken. A horizontal line P_(y) along the y-axis represents a location in which cross-sectional views in the z-y plane are taken.

With reference to FIG. 2D, a top view 200 d in the x-y plane of some alternative embodiments of the memory device of FIG. 2A is provided in which an inner surface of the third instantiation of the first multilayer stack 103 a is in contact with an outer perimeter of the first instantiation of the first multilayer stack 103 a.

With reference to FIG. 2E, a top view 200 e in the x-y plane of some alternative embodiments of the memory device of FIG. 2B is provided in which an inner surface of the magnetic layer 102 is in contact with an outer perimeter of the first instantiation of the second multilayer stack 103 b.

With reference to FIG. 2F, a top view 200 f in the x-y plane of some alternative embodiments of the memory device of FIG. 2C is provided in which an inner surface of the magnetic layer 102 is in contact with an outer perimeter of the first instantiation of the third multilayer stack 103 c.

Referring to FIG. 3A, a cross-sectional view 300 a in the z-x plane of some additional embodiments of the memory device at the vertical line P_(x) of FIG. 2D is provided in which the magnetic shielding structure 105 completely surrounds the chip 106. The electric connectors 108 extend from a PCB 101 and extend through the magnetic shielding structure 105 coupling to the chip 106. The insulating structure 120 envelopes the chip 106. An outer surface of the insulating structure 120 is separated from the inner surface of the magnetic shielding structure 105 by a non-zero distance in some embodiments, but in other embodiments the outer surface of the insulating structure 120 can be in direct contact with the inner surface of the magnetic shielding structure 105. The first instantiation of the first multilayer stack 103 a is disposed within the top region 122 above the upper surface of the chip 106. The second instantiation of the first multilayer stack 103 a is disposed within the bottom region 126 below the lower surface of the chip 106. The third instantiation of the first multilayer stack 103 a is disposed within the sidewall region 124 laterally offset from sidewalls of the chip 106.

A vertical distance 105 a between a bottom surface of the insulating structure 120 and a top surface of the multilayer stack 103 a in the bottom region 126 is within a range of approximately 0 mm to 1.25 mm. The vertical distance 105 a is also defined between a top surface of the insulating structure 120 and a bottom surface of the multilayer stack 103 a in the top region 122. A horizontal distance 105 b between a sidewall of the insulating structure 120 and a sidewall of the multilayer stack 103 a in the sidewall region 124 is within a range of approximately 0 mm to 1.25 mm. A width 105 d of the sidewall region 124 is within a range of approximately 0.05 μm to 1.25 cm. An opening distance 105 c is within a range of approximately 0.05 mm and 2.25 mm. In some embodiments, the insulating structure 120 does not exist and therefore distances such as vertical distance 105 a, and horizontal distance 105 b are relative to the chip 106.

Referring to FIG. 3B, a cross-sectional view 300 b in the z-x plane of some additional embodiments of the memory device at the vertical line P_(x) of FIG. 2E is provided in which the magnetic shielding structure 105 envelopes the chip 106. The electric connectors 108 extend from a PCB 101 and extend through the magnetic shielding structure 105 coupling to the chip 106. The insulating structure 120 envelopes the chip 106. An outer surface of the insulating structure 120 is laterally and vertically separated from the inner surface of the magnetic shielding structure 105 by a non-zero distance in some embodiments, but in other embodiments the outer surface of the insulating structure 120 can be in direct contact with the inner surface of the magnetic shielding structure 105. The first instantiation of the second multilayer stack 103 b is disposed within the top region 122 above the upper surface of the chip 106. The second instantiation of the second multilayer stack 103 b is disposed within the bottom region 126 below the lower surface of the chip 106. The magnetic layer 102 is disposed within the sidewall region 124 laterally offset from sidewalls of the chip 106.

Referring to FIG. 3C, a cross-sectional view 300 c in the z-x plane of some additional embodiments of the memory device at the vertical line P_(x) of FIG. 2F is provided in which the magnetic shielding structure 105 envelopes the chip 106. The electric connectors 108 extend from a PCB 101 and extend through the magnetic shielding structure 105 coupling to the chip 106. The insulating structure 120 envelopes the chip 106. An outer surface of the insulating structure 120 is laterally and vertically separated from the inner surface of the magnetic shielding structure 105 by a non-zero distance in some embodiments, but in other embodiments the outer surface of the insulating structure 120 can be in direct contact with the inner surface of the magnetic shielding structure 105. The first instantiation of the third multilayer stack 103 c is disposed within the top region 122 above the upper surface of the chip 106. The second instantiation of the third multilayer stack 103 c is disposed within the bottom region 126 below the lower surface of the chip 106. The magnetic layer 102 is disposed within the sidewall region 124 laterally offset from sidewalls of the chip 106.

Referring to FIG. 4A, a cross-sectional view 400 a in the z-y plane of some additional embodiments of the memory device at the horizontal line P_(y) of FIG. 2D is provided in which the magnetic shielding structure 105 completely surrounds the chip 106. The electric connectors 108 extend from a PCB 101 and extend through the magnetic shielding structure 105 coupling to the chip 106. The insulating structure 120 envelopes the chip 106. An outer surface of the insulating structure 120 is separated from the inner surface of the magnetic shielding structure 105 by a non-zero distance in some embodiments, but in other embodiments the outer surface of the insulating structure 120 can be in direct contact with the inner surface of the magnetic shielding structure 105. The first instantiation of the first multilayer stack 103 a is disposed within the top region 122 above the upper surface of the chip 106. The second instantiation of the first multilayer stack 103 a is disposed within the bottom region 126 below the lower surface of the chip 106. The third instantiation of the first multilayer stack 103 a is disposed within the sidewall region 124 laterally offset from sidewalls of the chip 106.

Referring to FIG. 4B, a cross-sectional view 400 b in the z-y plane of some additional embodiments of the memory device at the horizontal line P_(y) of FIG. 2E is provided in which the magnetic shielding structure 105 envelopes the chip 106. The electric connectors 108 extend from a PCB 101 and extend through the magnetic shielding structure 105 coupling to the chip 106. The insulating structure 120 envelopes the chip 106. An outer surface of the insulating structure 120 is laterally and vertically separated from the inner surface of the magnetic shielding structure 105 by a non-zero distance in some embodiments, but in other embodiments the outer surface of the insulating structure 120 can be in direct contact with the inner surface of the magnetic shielding structure 105. The first instantiation of the second multilayer stack 103 b is disposed within the top region 122 above the upper surface of the chip 106. The second instantiation of the second multilayer stack 103 b is disposed within the bottom region 126 below the lower surface of the chip 106. The magnetic layer 102 is disposed within the sidewall region 124 laterally offset from sidewalls of the chip 106.

Referring to FIG. 4C, a cross-sectional view 400 c in the z-y plane of some additional embodiments of the memory device at the horizontal line P_(y) of FIG. 2F is provided in which the magnetic shielding structure 105 envelopes the chip 106. The electric connectors 108 extend from a PCB 101 and extend through the magnetic shielding structure 105 coupling to the chip 106. The insulating structure 120 envelopes the chip 106. An outer surface of the insulating structure 120 is laterally and vertically separated from the inner surface of the magnetic shielding structure 105 by a non-zero distance in some embodiments, but in other embodiments the outer surface of the insulating structure 120 can be in direct contact with the inner surface of the magnetic shielding structure 105. The first instantiation of the third multilayer stack 103 c is disposed within the top region 122 above the upper surface of the chip 106. The second instantiation of the third multilayer stack 103 c is disposed within the bottom region 126 below the lower surface of the chip 106. The magnetic layer 102 is disposed within the sidewall region 124 laterally offset from sidewalls of the chip 106.

With reference to a range of values used for the vertical distance 105 a, horizontal distance 105 b, opening distance 105 c, and width 105 d described in relation to FIG. 3A above, it is to be understood that the range of values may be used with embodiments of the memory device in any one of the respectively labeled distances and/or widths of FIGS. 3B, 3C, 4A, 4B, and 4C.

With reference to FIGS. 5A and 6A, cross-sectional views 500 a and 600 a in the z-x plane and z-y plane of some alternative embodiments of the memory device of FIGS. 3A and 4A is provided respectively in which lower inner sidewalls of the magnetic shielding structure 105 are spaced apart from one another by an air gap within the magnetic shielding structure 105. In some embodiments, for example, the air gap exists in the bottom region 126 in place of the magnetic layer 102 and dielectric layer 104. Furthermore, in some embodiments, the second instantiation of the first multilayer stack 103 a is not within the bottom region 126.

With reference to FIGS. 5B and 6B, cross-sectional views 500 b and 600 b in the z-x plane and z-y plane of some alternative embodiments of the memory device of FIGS. 3B and 4B is provided respectively in which lower inner sidewalls of the magnetic shielding structure 105 are spaced apart from one another by an air gap within the magnetic shielding structure 105. In some embodiments, for example, the air gap exists in the bottom region 126 in place of the magnetic layer 102 and dielectric layer 104. Furthermore, in some embodiments, the second instantiation of the second multilayer stack 103 b is not within the bottom region 126.

With reference to FIGS. 5C and 6C, cross-sectional views 500 c and 600 c in the z-x plane and z-y plane of some alternative embodiments of the memory device of FIGS. 3C and 4C is provided respectively in which lower inner sidewalls of the magnetic shielding structure 105 are spaced apart from one another by an air gap within the magnetic shielding structure 105. In some embodiments, for example, the air gap exists in the bottom region 126 in place of the magnetic layer 102 and dielectric layer 104. Furthermore, in some embodiments, the second instantiation of the third multilayer stack 103 c is not within the bottom region 126.

With reference to FIGS. 5A-5C and 6A-6C in some embodiments, a support structure 502 is within the bottom region 126 supplying structural support to the magnetic shielding structure 105. The support structure 502 extends continuously between the lower inner sidewalls of the magnetic shielding structure 105 in the bottom region 126. The support structure 502 can comprise, for example, a dielectric sheet, an insulator sheet, or a thin metal layer. In some embodiments, there is no support structure 502.

With reference to FIGS. 7A and 8A, cross-sectional views 700 a and 800 a in the z-x plane and z-y plane of some alternative embodiments of the memory device of FIGS. 3A and 4A is provided respectively in which upper inner sidewalls of the magnetic shielding structure 105 are spaced apart from one another by an air gap within the magnetic shielding structure 105. In some embodiments, for example, the air gap exists in the top region 122 in place of the magnetic layer 102 and dielectric layer 104. Furthermore, in some embodiments, the first instantiation of the first multilayer stack 103 a is not within the top region 122.

With reference to FIGS. 7B and 8B, cross-sectional views 700 b and 800 b in the z-x plane and z-y plane of some alternative embodiments of the memory device of FIGS. 3B and 4B is provided respectively in which upper inner sidewalls of the magnetic shielding structure 105 are spaced apart from one another by an air gap within the magnetic shielding structure 105. In some embodiments, for example, the air gap exists in the top region 122 in place of the magnetic layer 102 and dielectric layer 104. Furthermore, in some embodiments, the first instantiation of the second multilayer stack 103 b is not within the top region 122.

With reference to FIGS. 7C and 8C, cross-sectional views 700 c and 800 c in the z-x plane and z-y plane of some alternative embodiments of the memory device of FIGS. 3C and 4C is provided respectively in which upper inner sidewalls of the magnetic shielding structure 105 are spaced apart from one another by an air gap within the magnetic shielding structure 105. In some embodiments, for example, the air gap exists in the top region 122 in place of the magnetic layer 102 and dielectric layer 104. Furthermore, in some embodiments, the first instantiation of the third multilayer stack 103 c is not within the top region 122.

With reference to FIGS. 7A-7C and 8A-8C in some embodiments, an upper support structure 702 is within the top region 122 supplying structural support to the magnetic shielding structure 105. The upper support structure 702 extends continuously between inner sidewalls of the sidewall region 124 defining a top surface of the magnetic shielding structure 105. The support structure 702 extends continuously between the upper inner sidewalls of the magnetic shielding structure 105 in the top region 122. The upper support structure 702 can comprise, for example, a dielectric sheet, an insulator sheet, or a thin metal layer. In some embodiments, there is no upper support structure 702.

With reference to FIGS. 9A and 10A, cross-sectional views 900 a and 1000 a in the z-x plane and z-y plane of some alternative embodiments of the memory device of FIGS. 3A and 4A is provided respectively in which an upper inner surface and a lower inner surface of the magnetic shielding structure 105 are spaced apart from one another by an air gap within the magnetic shielding structure 105. In some embodiments, for example, the air gap exists in a top portion 124 a of the sidewall region 124 in place of the magnetic layer 102 and dielectric layer 104. Furthermore, in some embodiments, a portion of the third instantiation of the first multilayer stack 103 a is not within the top portion 124 a of the sidewall region 124.

With reference to FIGS. 9B and 10B, cross-sectional views 900 b and 1000 b in the z-x plane and z-y plane of some alternative embodiments of the memory device of FIGS. 3B and 4B is provided respectively in which an upper inner surface and a lower inner surface of the magnetic shielding structure 105 are spaced apart from one another by an air gap within the magnetic shielding structure 105. In some embodiments, for example, the air gap exists in a top portion 124 a of the sidewall region 124 in place of the magnetic layer 102. Furthermore, in some embodiments, a portion of the magnetic layer 102 is not within the top portion 124 a of the sidewall region 124.

With reference to FIGS. 9C and 10C, cross-sectional views 900 c and 1000 c in the z-x plane and z-y plane of some alternative embodiments of the memory device of FIGS. 3C and 4C is provided respectively in which an upper inner surface and a lower inner surface of the magnetic shielding structure 105 are spaced apart from one another by an air gap within the magnetic shielding structure 105. In some embodiments, for example, the air gap exists in a top portion 124 a of the sidewall region 124 in place of the magnetic layer 102. Furthermore, in some embodiments, a portion of the magnetic layer 102 is not within the top portion 124 a of the sidewall region 124.

With reference to FIGS. 9A-9C and 10A-10C in some embodiments, a support structure 902 is within the top portion 124 a of the sidewall region 124 supplying structural support to the magnetic shielding structure 105. The support structure 902 extends continuously between a bottom portion 124 b of the sidewall region 124 to the top region 122. The support structure 902 extends continuously between the upper inner surface and lower inner surface of the magnetic shielding structure 105 in the top portion 124 a of the sidewall region 124. The support structure 902 can comprise, for example, a dielectric sheet, an insulator sheet, or a thin metal layer. In some embodiments, there is no support structure 902. In some embodiments, the first instantiation of the first, second, and third multilayer stack 103 a, 103 b, and 103 c respectively extend between outer sidewalls of the sidewall region 124. Where outer sidewalls of the respective first instantiation of the first, second, and third multilayer stack 103 a, 103 b, and 103 c are aligned with outer sidewalls of a bottom surface of the magnetic shielding structure 105. In some embodiments, the first instantiation of the first, second, and third multilayer stack 103 a, 103 b, and 103 c is respectively confined within the top region 122 and does not extend to the sidewall region 124.

With reference to FIGS. 11A and 12A, cross-sectional views 1100 a and 1200 a in the z-x plane and z-y plane of some alternative embodiments of the memory device of FIGS. 3A and 4A is provided respectively in which an upper inner surface and a lower inner surface of the magnetic shielding structure 105 are spaced apart from one another by an air gap within the magnetic shielding structure 105. In some embodiments, for example, the air gap exists in a bottom portion 124 b of the sidewall region 124 in place of the magnetic layer 102 and dielectric layer 104. Furthermore, in some embodiments, a portion of the third instantiation of the first multilayer stack 103 a is not within the bottom portion 124 b of the sidewall region 124.

With reference to FIGS. 11B and 12B, cross-sectional views 1100 b and 1200 b in the z-x plane and z-y plane of some alternative embodiments of the memory device of FIGS. 3B and 4B is provided respectively in which an upper inner surface and a lower inner surface of the magnetic shielding structure 105 are spaced apart from one another by an air gap within the magnetic shielding structure 105. In some embodiments, for example, the air gap exists in a bottom portion 124 b of the sidewall region 124 in place of the magnetic layer 102. Furthermore, in some embodiments, a portion of the magnetic layer 102 is not within the bottom portion 124 b of the sidewall region 124.

With reference to FIGS. 11C and 12C, cross-sectional views 1100 c and 1200 c in the z-x plane and z-y plane of some alternative embodiments of the memory device of FIGS. 3C and 4C is provided respectively in which an upper inner surface and a lower inner surface of the magnetic shielding structure 105 are spaced apart from one another by an air gap within the magnetic shielding structure 105. In some embodiments, for example, the air gap exists in a bottom portion 124 b of the sidewall region 124 in place of the magnetic layer 102. Furthermore, in some embodiments, a portion of the magnetic layer 102 is not within the bottom portion 124 b of the sidewall region 124.

With reference to FIGS. 11A-11C and 12A-12C in some embodiments, a side support structure 1102 is within the bottom portion 124 b of the sidewall region 124 supplying structural support to the magnetic shielding structure 105. The side support structure 1102 extends continuously between a top portion 124 a of the sidewall region 124 and the bottom region 126. In some embodiments, the side support structure 1102 extends continuously between the upper inner surface and lower inner surface of the magnetic shielding structure 105 in the bottom portion 124 b of the sidewall region 124. The side support structure 1102 can comprise, for example, a dielectric sheet, an insulator sheet, or a thin metal layer. In some embodiments, there is no side support structure 1102. In some embodiments, the second instantiation of the first, second, and third multilayer stack 103 a, 103 b, and 103 c respectively extend between outer sidewalls of the sidewall region 124. Where outer sidewalls of the respective second instantiation of the first, second, and third multilayer stack 103 a, 103 b, and 103 c are aligned with outer sidewalls of a top surface of the magnetic shielding structure 105. In some embodiments, the second instantiation of the first, second, and third multilayer stack 103 a, 103 b, and 103 c is respectively confined within the bottom region 126 and does not extend to the sidewall region 124.

With reference to FIGS. 13A and 14A, cross-sectional views 1300 a and 1400 a in the z-x plane and z-y plane of some alternative embodiments of the memory device of FIGS. 3A and 4A is provided respectively in which an upper inner surface and a lower inner surface of the magnetic shielding structure 105 are spaced apart from one another by a first air gap within the magnetic shielding structure 105. Inner sidewalls of the magnetic shielding structure 105 are spaced apart from one another by a second air gap within the magnetic shielding structure 105. In some embodiments, for example, the first air gap exists in a top portion 124 a of the sidewall region 124 and the second air gap exists in the bottom region 126 in place of the magnetic layer 102 and dielectric layer 104. Furthermore, in some embodiments, a portion of the third instantiation of the first multilayer stack 103 a is not within the top portion 124 a of the sidewall region 124 and the second instantiation of the first multilayer stack 103 a is not within the bottom region 126.

With reference to FIGS. 13B and 14B, cross-sectional views 1300 b and 1400 b in the z-x plane and z-y plane of some alternative embodiments of the memory device of FIGS. 3B and 4B is provided respectively in which an upper inner surface and a lower inner surface of the magnetic shielding structure 105 are spaced apart from one another by a first air gap within the magnetic shielding structure 105. Inner sidewalls of the magnetic shielding structure 105 are spaced apart from one another by a second air gap within the magnetic shielding structure 105. In some embodiments, for example, the first air gap exists in a top portion 124 a of the sidewall region 124 and the second air gap exists in the bottom region 126 in place of the magnetic layer 102. Furthermore, in some embodiments, a portion of the magnetic layer 102 is not within the top portion 124 a of the sidewall region 124 and the second instantiation of the second multilayer stack 103 b is not within the bottom region 126.

With reference to FIGS. 13C and 14C, cross-sectional views 1300 c and 1400 c in the z-x plane and z-y plane of some alternative embodiments of the memory device of FIGS. 3C and 4C is provided respectively in which an upper inner surface and a lower inner surface of the magnetic shielding structure 105 are spaced apart from one another by a first air gap within the magnetic shielding structure 105. Inner sidewalls of the magnetic shielding structure 105 are spaced apart from one another by a second air gap within the magnetic shielding structure 105. In some embodiments, for example, the first air gap exists in a top portion 124 a of the sidewall region 124 and the second air gap exists in the bottom region 126 in place of the magnetic layer 102. Furthermore, in some embodiments, a portion of the magnetic layer 102 is not within the top portion 124 a of the sidewall region 124 and the second instantiation of the third multilayer stack 103 c is not within the bottom region 126.

With reference to FIGS. 13A-13C and 14A-14C in some embodiments, a first support structure 1302 is within the top portion 124 a of the sidewall region 124 supplying structural support to the magnetic shielding structure 105. The first support structure 1302 extends continuously between a bottom portion 124 b of the sidewall region 124 to the top region 122. A second support structure 1304 is within the bottom region 126 supplying structural support to the magnetic shielding structure 105. In some embodiments, the first support structure 1302 extends continuously between the upper inner surface and lower inner surface of the magnetic shielding structure 105 in the top portion 124 a of the sidewall region 124. In some embodiments, the second support structure 1304 extends continuously between inner sidewalls of the magnetic shielding structure 105 in the bottom region 126. The second support structure 1304 extends continuously between inner sidewalls of the sidewall region 124. The first support structure 1302 and second support structure 1304 can comprise, for example, a dielectric sheet, an insulator sheet, or a thin metal layer. In some embodiments, there is no first support structure 1302 and/or second support structure 1304. In some embodiments, the first instantiation of the first, second, and third multilayer stack 103 a, 103 b, and 103 c respectively extend between outer sidewalls of the sidewall region 124. Where outer sidewalls of the respective second instantiation of the first, second, and third multilayer stack 103 a, 103 b, and 103 c are aligned with outer sidewalls of a bottom surface of the magnetic shielding structure 105. In some embodiments, the first instantiation of the first, second, and third multilayer stack 103 a, 103 b, and 103 c is respectively confined within the top region 122 and does not extend to the sidewall region 124.

With reference to FIGS. 15A and 16A, cross-sectional views 1500 a and 1600 a in the z-x plane and z-y plane of some alternative embodiments of the memory device of FIGS. 3A and 4A is provided respectively in which an upper inner surface of the magnetic shielding structure 105 is spaced apart from a top surface of the PCB 101 by an air gap. In some embodiments, for example, the air gap exists in a bottom portion 124 b of the sidewall region 124 and the bottom region 126 in place of the magnetic layer 102 and dielectric layer 104. Furthermore, in some embodiments, a portion of the third instantiation of the first multilayer stack 103 a is not within the bottom portion 124 b of the sidewall region 124 and the second instantiation of the first multilayer stack 103 a is not within the bottom region 126.

With reference to FIGS. 15B and 16B, cross-sectional views 1500 b and 1600 b in the z-x plane and z-y plane of some alternative embodiments of the memory device of FIGS. 3B and 4B is provided respectively in which an upper inner surface of the magnetic shielding structure 105 is spaced apart from a top surface of the PCB 101 by an air gap. In some embodiments, for example, the air gap exists in a bottom portion 124 b of the sidewall region 124 and the bottom region 126 in place of the magnetic layer 102 and dielectric layer 104. Furthermore, in some embodiments, a portion of the magnetic layer 102 is not within the bottom portion 124 b of the sidewall region 124 and the second instantiation of the second multilayer stack 103 b is not within the bottom region 126.

With reference to FIGS. 15C and 16C, cross-sectional views 1500 c and 1600 c in the z-x plane and z-y plane of some alternative embodiments of the memory device of FIGS. 3C and 4C is provided respectively in which an upper inner surface of the magnetic shielding structure 105 is spaced apart from a top surface of the PCB 101 by an air gap. In some embodiments, for example, the air gap exists in a bottom portion 124 b of the sidewall region 124 and the bottom region 126 in place of the magnetic layer 102 and dielectric layer 104. Furthermore, in some embodiments, a portion of the magnetic layer 102 is not within the bottom portion 124 b of the sidewall region 124 and the second instantiation of the third multilayer stack 103 c is not within the bottom region 126.

With reference to FIGS. 15A-15C and 16A-16C in some embodiments, a support structure 1502 is within the bottom portion 124 b of the sidewall region 124 and the bottom region 126 supplying structural support to the magnetic shielding structure 105. The support structure 1502 extends continuously between outer sidewalls of the top portion 124 a of the sidewall region 124. In some embodiments, the support structure 1502 extends continuously between a first sidewall 1504 of the magnetic shielding structure 105 and a second sidewall 1506 of the magnetic shielding structure 105 in the bottom portion 124 b of the sidewall region 124 and bottom region 126. The support structure 1502 can comprise, for example, a dielectric sheet, an insulator sheet, or a thin metal layer. In some embodiments, there is no support structure 1502.

With reference to FIGS. 17A and 18A, cross-sectional views 1700 a and 1800 a in the z-x plane and z-y plane of some alternative embodiments of the memory device of FIGS. 3A and 4A is provided respectively in which an upper inner surface of the magnetic shielding structure 105 is spaced apart from a bottom inner surface of the magnetic shielding structure 105 by a first air gap. Upper inner sidewalls of the magnetic shielding structure 105 are spaced apart by a second air gap. In some embodiments, for example, the first air gap exists in a bottom portion 124 b of the sidewall region 124 and the second air gap exists in a top region 122 in place of the magnetic layer 102 and dielectric layer 104. Furthermore, in some embodiments, a portion of the third instantiation of the first multilayer stack 103 a is not within the bottom portion 124 b of the sidewall region 124 and the first instantiation of the first multilayer stack 103 a is not within the top region 122.

With reference to FIGS. 17B and 18B, cross-sectional views 1700 b and 1800 b in the z-x plane and z-y plane of some alternative embodiments of the memory device of FIGS. 3B and 4B is provided respectively in which an upper inner surface of the magnetic shielding structure 105 is spaced apart from a bottom inner surface of the magnetic shielding structure 105 by a first air gap. Upper inner sidewalls of the magnetic shielding structure 105 are spaced apart by a second air gap. In some embodiments, for example, the first air gap exists in a bottom portion 124 b of the sidewall region 124 and the second air gap exists in a top region 122 in place of the magnetic layer 102. Furthermore, in some embodiments, a portion of the magnetic layer 102 is not within the bottom portion 124 b of the sidewall region 124 and the first instantiation of the second multilayer stack 103 b is not within the top region 122.

With reference to FIGS. 17C and 18C, cross-sectional views 1700 c and 1800 c in the z-x plane and z-y plane of some alternative embodiments of the memory device of FIGS. 3C and 4C is provided respectively in which an upper inner surface of the magnetic shielding structure 105 is spaced apart from a bottom inner surface of the magnetic shielding structure 105 by a first air gap. Upper inner sidewalls of the magnetic shielding structure 105 are spaced apart by a second air gap. In some embodiments, for example, the first air gap exists in a bottom portion 124 b of the sidewall region 124 and the second air gap exists in a top region 122 in place of the magnetic layer 102. Furthermore, in some embodiments, a portion of the magnetic layer 102 is not within the bottom portion 124 b of the sidewall region 124 and the first instantiation of the third multilayer stack 103 c is not within the top region 122.

With reference to FIGS. 17A-17C and 18A-18C in some embodiments, the upper support structure 702 is within the top region 122 supplying structural support to the magnetic shielding structure 105. The side support structure 1102 is within the bottom portion 124 b of the sidewall region 124 supplying structural support to the magnetic shielding structure 105. In some embodiments, there is no upper support structure 702 and/or side support structure 1102. In some embodiments, the side support structure 1102 extends continuously between the upper inner surface and lower inner surface of the magnetic shielding structure 105 in the bottom portion 124 b of the sidewall region 124. In some embodiments, the upper support structure 702 extends continuously between inner sidewalls of the magnetic shielding structure 105 in the top region 122. In some embodiments, the second instantiation of the first, second, and third multilayer stack 103 a, 103 b, and 103 c respectively extend between outer sidewalls of the sidewall region 124. Where outer sidewalls of the respective second instantiation of the first, second, and third multilayer stack 103 a, 103 b, and 103 c are aligned with outer sidewalls of a top surface of the magnetic shielding structure 105. In some embodiments, the second instantiation of the first, second, and third multilayer stack 103 a, 103 b, and 103 c is respectively confined within the bottom region 126 and does not extend to the sidewall region 124.

With reference to FIGS. 19A and 20A, cross-sectional views 1900 a and 2000 a in the z-x plane and z-y plane of some alternative embodiments of the memory device of FIGS. 3A and 4A is provided respectively in which an upper surface of the chip 106 is covered by an air gap and not covered by the magnetic shielding structure 105. In some embodiments, for example, the air gap exists in a top portion 124 a of the sidewall region 124 and the top region 122 in place of the magnetic layer 102 and dielectric layer 104. Furthermore, in some embodiments, a portion of the third instantiation of the first multilayer stack 103 a is not within the top portion 124 a of the sidewall region 124 and the first instantiation of the first multilayer stack 103 a is not within the top region 122.

With reference to FIGS. 19B and 20B, cross-sectional views 1900 b and 2000 b in the z-x plane and z-y plane of some alternative embodiments of the memory device of FIGS. 3B and 4B is provided respectively in which an upper surface of the chip 106 is covered by an air gap and not covered by the magnetic shielding structure 105. In some embodiments, for example, the air gap exists in a top portion 124 a of the sidewall region 124 and the top region 122 in place of the magnetic layer 102 and dielectric layer 104. Furthermore, in some embodiments, a portion of the magnetic layer 102 is not within the top portion 124 a of the sidewall region 124 and the first instantiation of the second multilayer stack 103 b is not within the top region 122.

With reference to FIGS. 19C and 20C, cross-sectional views 1900 c and 2000 c in the z-x plane and z-y plane of some alternative embodiments of the memory device of FIGS. 3C and 4C is provided respectively in which an upper surface of the chip 106 is covered by an air gap and not covered by the magnetic shielding structure 105. In some embodiments, for example, the air gap exists in a top portion 124 a of the sidewall region 124 and the top region 122 in place of the magnetic layer 102 and dielectric layer 104. Furthermore, in some embodiments, a portion of the magnetic layer 102 is not within the top portion 124 a of the sidewall region 124 and the first instantiation of the third multilayer stack 103 c is not within the top region 122.

With reference to FIGS. 19A-19C and 20A-20C in some embodiments, a top surface support structure 1902 is within the top portion 124 a of the sidewall region 124 and the top region 122 supplying structural support to the magnetic shielding structure 105. The top surface support structure 1902 extends continuously between outer sidewalls of the bottom portion 124 b of the sidewall region 124. In some embodiments, the top surface support structure 1902 extends continuously between a first sidewall 1904 of the magnetic shielding structure 105 and a second sidewall 1906 of the magnetic shielding structure 105 in the top portion 124 a of the sidewall region 124 and top region 122. The top surface support structure 1902 can comprise, for example, a dielectric sheet, an insulator sheet, or a thin metal layer. In some embodiments, there is no top surface support structure 1902. In some embodiments, the second instantiation of the first, second, and third multilayer stack 103 a, 103 b, and 103 c respectively extend between outer sidewalls of the sidewall region 124. Where outer sidewalls of the respective second instantiation of the first, second, and third multilayer stack 103 a, 103 b, and 103 c are aligned with outer sidewalls of the magnetic shielding structure 105. In some embodiments, the second instantiation of the first, second, and third multilayer stack 103 a, 103 b, and 103 c is respectively confined within the bottom region 126 and does not extend to the sidewall region 124.

With reference to FIGS. 21A and 22A, cross-sectional views 2100 a and 2200 a in the z-x plane and z-y plane of some alternative embodiments of the memory device of FIGS. 3A and 4A is provided respectively in which an upper inner surface of the magnetic shielding structure 105 is separated from a bottom inner surface of the magnetic shielding structure 105 by an air gap. In some embodiments, for example, the air gap exists in the sidewall region 124 in place of the magnetic layer 102 and dielectric layer 104. Furthermore, in some embodiments, the third instantiation of the first multilayer stack 103 a is not within the sidewall region 124.

With reference to FIGS. 21B and 22B, cross-sectional views 2100 b and 2200 b in the z-x plane and z-y plane of some alternative embodiments of the memory device of FIGS. 3B and 4B is provided respectively in which an upper inner surface of the magnetic shielding structure 105 is separated from a bottom inner surface of the magnetic shielding structure 105 by an air gap. In some embodiments, for example, the air gap exists in the sidewall region 124 in place of the magnetic layer 102. Furthermore, in some embodiments, the magnetic layer 102 is not within the sidewall region 124.

With reference to FIGS. 21C and 22C, cross-sectional views 2100 c and 2200 c in the z-x plane and z-y plane of some alternative embodiments of the memory device of FIGS. 3C and 4C is provided respectively in which an upper inner surface of the magnetic shielding structure 105 is separated from a bottom inner surface of the magnetic shielding structure 105 by an air gap. In some embodiments, for example, the air gap exists in the sidewall region 124 in place of the magnetic layer 102. Furthermore, in some embodiments, the magnetic layer 102 is not within the sidewall region 124.

With reference to FIGS. 21A-21C and 22A-22C in some embodiments, a sidewall support structure 2102 is within the sidewall region 124 supplying structural support to the magnetic shielding structure 105. The sidewall support structure 2102 extends continuously between the top region 122 and the bottom region 126. In some embodiments, the sidewall support structure 2102 extends continuously between the bottom inner surface and upper inner surface of the magnetic shielding structure 105 in the sidewall region 124. The sidewall support structure 2102 can comprise, for example, a dielectric sheet, an insulator sheet, or a thin metal layer. In some embodiments, there is no sidewall support structure 2102. In some embodiments, the first and second instantiations of the first, second, and third multilayer stack 103 a, 103 b, and 103 c respectively extend between outer sidewalls of the sidewall region 124. Where outer sidewalls of the respective first and second instantiations of the first, second, and third multilayer stack 103 a, 103 b, and 103 c are aligned with outer sidewalls of the magnetic shielding structure 105. In some embodiments, the first and second instantiations of the first, second, and third multilayer stack 103 a, 103 b, and 103 c are respectively confined within the top region 122 and the bottom region 126 and do not extend to the sidewall region 124.

With reference to FIGS. 23A and 24A, cross-sectional views 2300 a and 2400 a in the z-x plane and z-y plane of some alternative embodiments of the memory device of FIGS. 3A and 4A is provided respectively in which an upper inner surface of the magnetic shielding structure 105 is separated from the PCB 101 by an air gap. In some embodiments, for example, the air gap exists in the sidewall region 124 and bottom region 126 in place of the magnetic layer 102 and dielectric layer 104. Furthermore, in some embodiments, the third instantiation of the first multilayer stack 103 a is not within the sidewall region 124 and the second instantiation of the first multilayer stack 103 a is not within the bottom region 126.

With reference to FIGS. 23B and 24B, cross-sectional views 2300 b and 2400 b in the z-x plane and z-y plane of some alternative embodiments of the memory device of FIGS. 3B and 4B is provided respectively in which an upper inner surface of the magnetic shielding structure 105 is separated from the PCB 101 by an air gap. In some embodiments, for example, the air gap exists in the sidewall region 124 and bottom region 126 in place of the magnetic layer 102 and dielectric layer 104. Furthermore, in some embodiments, the magnetic layer 102 is not within the sidewall region 124 and the second instantiation of the second multilayer stack 103 b is not within the bottom region 126.

With reference to FIGS. 23C and 24C, cross-sectional views 2300 c and 2400 c in the z-x plane and z-y plane of some alternative embodiments of the memory device of FIGS. 3C and 4C is provided respectively in which an upper inner surface of the magnetic shielding structure 105 is separated from the PCB 101 by an air gap. In some embodiments, for example, the air gap exists in the sidewall region 124 and bottom region 126 in place of the magnetic layer 102 and dielectric layer 104. Furthermore, in some embodiments, the magnetic layer 102 is not within the sidewall region 124 and the second instantiation of the third multilayer stack 103 c is not within the bottom region 126.

With reference to FIGS. 23A-23C and 24A-24C in some embodiments, a lower surface support structure 2302 is within the sidewall region 124 and bottom region 126 supplying structural support to the magnetic shielding structure 105. The lower surface support structure 2302 extends continuously between outer sidewalls of the top region 122. In some embodiments, the lower surface support structure 2302 extends continuously between a first sidewall 2304 of the magnetic shielding structure 105 and a second sidewall 2306 of the magnetic shielding structure 105 in the sidewall region 124 and bottom region 126. The lower surface support structure 2302 can comprise, for example, a dielectric sheet, an insulator sheet, or a thin metal layer. In some embodiments, there is no lower surface support structure 2302. In some embodiments, the first instantiation of the first, second, and third multilayer stack 103 a, 103 b, and 103 c respectively extends between outer sidewalls of the sidewall region 124. Where outer sidewalls of the first instantiation of the first, second, and third multilayer stack 103 a, 103 b, and 103 c are aligned with outer sidewalls of the magnetic shielding structure 105. In some embodiments, the first instantiation of the first, second, and third multilayer stack 103 a, 103 b, and 103 c is respectively confined within the top region 122 and does not extend to the sidewall region 124.

With reference to FIGS. 25A and 26A, cross-sectional views 2500 a and 2600 a in the z-x plane and z-y plane of some alternative embodiments of the memory device of FIGS. 3A and 4A is provided respectively in which an upper surface of the chip 106 is covered by an air gap and not covered by the magnetic shielding structure 105. In some embodiments, for example, the air gap exists in the sidewall region 124 and the top region 122 in place of the magnetic layer 102 and dielectric layer 104. Furthermore, in some embodiments, the third instantiation of the first multilayer stack 103 a is not within the sidewall region 124 and the first instantiation of the first multilayer stack 103 a is not within the top region 122.

With reference to FIGS. 25B and 26B, cross-sectional views 2500 b and 2600 b in the z-x plane and z-y plane of some alternative embodiments of the memory device of FIGS. 3B and 4B is provided respectively in which an upper surface of the chip 106 is covered by an air gap and not covered by the magnetic shielding structure 105. In some embodiments, for example, the air gap exists in the sidewall region 124 and the top region 122 in place of the magnetic layer 102 and dielectric layer 104. Furthermore, in some embodiments, the magnetic layer 102 is not within the sidewall region 124 and the first instantiation of the second multilayer stack 103 b is not within the top region 122.

With reference to FIGS. 25C and 26C, cross-sectional views 2500 c and 2600 c in the z-x plane and z-y plane of some alternative embodiments of the memory device of FIGS. 3C and 4C is provided respectively in which an upper surface of the chip 106 is covered by an air gap and not covered by the magnetic shielding structure 105. In some embodiments, for example, the air gap exists in the sidewall region 124 and the top region 122 in place of the magnetic layer 102 and dielectric layer 104. Furthermore, in some embodiments, the magnetic layer 102 is not within the sidewall region 124 and the first instantiation of the third multilayer stack 103 c is not within the top region 122.

With reference to FIGS. 25A-25C and 26A-26C in some embodiments, an upper surface support structure 2502 is within the sidewall region 124 and top region 122 supplying structural support to the magnetic shielding structure 105. The upper surface support structure 2502 extends continuously between outer sidewalls of the bottom region 126. In some embodiments, the upper surface support structure 2502 extends continuously between a first sidewall 2504 of the magnetic shielding structure 105 and a second sidewall 2506 of the magnetic shielding structure 105 in the sidewall region 124 and top region 122. The upper surface support structure 2502 can comprise, for example, a dielectric sheet, an insulator sheet, or a thin metal layer. In some embodiments, there is no upper surface support structure 2502. In some embodiments, the second instantiation of the first, second, and third multilayer stack 103 a, 103 b, and 103 c respectively extends between outer sidewalls of the sidewall region 124. Where outer sidewalls of the second instantiation of the first, second, and third multilayer stack 103 a, 103 b, and 103 c is aligned with outer sidewalls of the magnetic shielding structure 105. In some embodiments, the second instantiation of the first, second, and third multilayer stack 103 a, 103 b, and 103 c is respectively confined within the bottom region 126 and does not extend to the sidewall region 124.

With reference to FIGS. 3A-3C and 4A-4C and any embodiments of FIGS. 3A-3C and 4A-4C, it can be appreciated that any air gap (e.g. an air gap, first air gap, second air gap, etc.) can comprise air and/or materials from the insulating structure 120.

With reference to FIGS. 27, 28A, 28B, 29, 30A, 30B, 31, 32A, and 32B, cross-sectional views 2700, 2800 a, 2800 b, 2900, 3000 a, 3000 b, 3100, 3200 a, and 3200 b of various embodiments of a method for forming sections of a magnetic field shielding structure are provided. The method is illustrated using embodiments of the memory device in FIGS. 3A-3B and 4A-4B. Notwithstanding this, the method may be used to form embodiments of the memory device in any one of FIGS. 5A-5C, 6A-6C, 7A-7C, 8A-8C, 9A-9C, 10A-10C, 11A-11C, 12A-12C, 13A-13C, 14A-14C, 15A-15C, 16A-16C, 17A-17C, 18A-18C, 19A-19C, 20A-20C, 21A-21C, 22A-22C, 23A-23C, 24A-24C, 25A-25C, and 26A-26C. Additionally, as seen hereafter, FIGS. 27, 28A, and 28B correspond to a method for forming the first multilayer stack 103 a. FIGS. 27, 28A, 28B, 29, 30A, and 30B correspond to a method for forming the second multilayer stack 103 b. FIGS. 27, 28A, 28B, 29, 30A, 30B, 31, 32A, and 32B correspond to a method for forming the third multilayer stack 103 c.

Although the cross-sectional views 2700, 2800 a, 2800 b, 2900, 3000 a, 3000 b, 3100, 3200 a, and 3200 b shown in FIGS. 27, 28A, 28B, 29, 30A, 30B, 31, 32A, and 32B are described with reference to a method, it will be appreciated that the structures shown in FIGS. 27, 28A, 28B, 29, 30A, 30B, 31, 32A, and 32B are not limited to the method but rather may stand alone separate of the method. Although FIGS. 27, 28A, 28B, 29, 30A, 30B, 31, 32A, and 32B are described as a series of acts, it will be appreciated that these acts are not limiting in that the order of the acts can be altered in other embodiments, and the methods disclosed are also applicable to other structures. In other embodiments, some acts that are illustrated and/or described may be omitted in whole or in part.

As illustrated by the perspective view, with the front portions removed, 2700 of FIG. 27 , a magnetic layer 102 (in some embodiments a foil/strip or plate) and a dielectric layer 104 (in some embodiments a foil/strip or plate) are laminated/coated with an adhesive layer (not shown). In some embodiments, the adhesive layer is a foil, strip, or plate that overlies the magnetic layer 102 and the dielectric layer 104, respectively. In yet other embodiments, a substantially thin layer of the adhesive layer completely envelopes the magnetic layer 102 and the dielectric layer 104, respectively. In some embodiments, the adhesive layer is an insulating adhesive layer. A first pair of layers 2702 is defined by a single magnetic layer 102 and a single dielectric layer 104.

As illustrated by the perspective view, with the front portions removed, 2800 a of FIG. 28A, at least one or more pairs of the adhesive laminated magnetic layer 102 and adhesive laminated dielectric layer 104 are formed over the first pair of layers 2702. A last adhesive laminated magnetic layer 102 is formed over the at least one or more pairs of the adhesive laminated magnetic layer 102 and adhesive laminated dielectric layer 104. A stack of layers 2802 is defined by the last adhesive laminated magnetic layer 102 overlaying the at least one or more pairs of the adhesive laminated magnetic layer 102 and adhesive laminated dielectric layer 104.

As illustrated by the perspective view, with the front portions removed, 2800 b of FIG. 28B, the stack of layers (2802 of FIG. 28A) are attached to the first pair of layers (2702 of FIG. 28A) defining a first multilayer sheet 2804. A top surface 2804 a of the first multilayer sheet 2804 is defined by a top surface of the last adhesive laminated magnetic layer 102 (of FIG. 28A). A bottom surface 2804 b of the first multilayer sheet 2804 is defined by a bottom surface of the magnetic layer 102 of the first pair of layers (2702 of FIG. 28A). The length L₁ of the first multilayer sheet 2804 is within a range of approximately 4 millimeters to approximately 10 centimeters, and the width W₁ of the first multilayer sheet 2804 is within a range of approximately 4 millimeters to approximately 10 centimeters, or some other suitable value, for example. In some embodiments, the length and width L₁, W₁ of the first multilayer sheet 2804 respectively are formed to values suitable for the first multilayer stack 103 a. In yet other embodiments, the length and width L₁, W₁ of the first multilayer sheet 2804 respectively are formed to values substantially greater than the first multilayer stack 103 a. In some embodiments, the first multilayer sheet 2804 comprises at least three or more magnetic layers 102 and three or more dielectric layers 104.

A thickness T_(m) defines the thickness of each magnetic layer 102 in the first multilayer sheet 2804. The thickness T_(m) is within a range of approximately 10 micrometers to approximately 1,000 micrometers, or some other suitable value. In some embodiments, the thickness T_(m) is the same for each magnetic layer 102 in the first multilayer sheet 2804. In some embodiments, the thickness T_(m) is the same for a first plurality of magnetic layers 102 in the first multilayer sheet 2804 and different for a second plurality of magnetic layers 102 in the first multilayer sheet 2804. In yet another embodiment, the magnetic layer 102 of the first pair of layers (2702 of FIG. 28A) is substantially thicker than the thickness of the magnetic layers 102 in the stack of layers (2802 of FIG. 28A). The magnetic layer 102 may be or comprise, for example, iron (Fe), cobalt (Co), nickel (Ni), some other magnetic material, some other conductive material, or the like.

A thickness T_(d) defines the thickness of each dielectric layer 104 in the first multilayer sheet 2804. The thickness T_(d) is within a range of approximately 10 nanometers to approximately 1,000 micrometers, or some other suitable value. In some embodiments, the thickness T_(d) is the same for each dielectric layer 104 in the first multilayer sheet 2804. In some embodiments, the thickness T_(d) is the same for a first plurality of dielectric layers 104 in the first multilayer sheet 2804 and different for a second plurality of dielectric layers 104 in the first multilayer sheet 2804. In yet another embodiment, the dielectric layer 104 of the first pair of layers (2702 of FIG. 28A) is substantially thicker than the thickness of the dielectric layers 104 in the stack of layers (2802 of FIG. 28A). The dielectric layer 104 may be or comprise, for example, a low κ dielectric, silicon oxide, a high κ dielectric, some other dielectric, or any combination of the foregoing.

As illustrated by the perspective view, with the front portions removed, 2900 of FIG. 29 , a distance D_(d) is set from an outer edge of the first multilayer sheet 2804 defining a first cut line 2902. The distance D_(d) is within a range of approximately 1 micrometer to 10,000 micrometers, approximately 1 micrometer to 5,000 micrometers, approximately 5,000 micrometers to 10,000 micrometers, or some other suitable value.

As illustrated by the perspective view, with the front portions removed, 3000 a of FIG. 30A, the first multilayer sheet (2804 of FIG. 29 ) is tailored (or cut) along the first cut line (2902 of FIG. 29 ) defining a second multilayer sheet 3002. The distance D_(d) defines a width of the second multilayer sheet 3002.

As illustrated by the perspective view, with the front portions removed, 3000 b of FIG. 30B, the second multilayer sheet 3002 (of FIG. 30A) is rotated 90 degrees. A top surface 3002 a of the second multilayer sheet 3002 comprises a top surface of a plurality of strips of the magnetic layer 102 and dielectric layer 104. A bottom surface 3002 b of the second multilayer sheet 3002 comprises a bottom surface of the plurality of strips of the magnetic layer 102 and dielectric layer 104. In some embodiments, the second multilayer sheet 3002 comprises at least three or more magnetic strips 102 and two or more dielectric strips 104. In some embodiments, the second multilayer sheet 3002 defines the second multilayer stack 103 b.

As illustrated by the perspective view, with the front portions removed, 3100 of FIG. 31 , a plurality of M (a number greater than 2) first multilayer sheet (2804 of FIG. 29 ) are disposed between M−1 adhesive laminated dielectric layers 104. The plurality of M first multilayer sheet 2804 are attached (or glued) to the respective M−1 adhesive laminated dielectric layers 104. In some embodiments, M is a number equal to or greater than 4. A distance Da is set from an outer edge of the plurality of M first multilayer sheet 2804 defining a second cut line 3102. The distance Da is within a range of approximately 10 micrometers to approximately 10,000 micrometers, or some other suitable value. A thickness L₁ of each of the M−1 adhesive laminated dielectric layers 104 are respectively within a range of approximately 10 nanometers to approximately 1,000 micrometers, or some other suitable value.

As illustrated by the perspective view, with the front portions removed, 3200 a of FIG. 32A, the plurality of M first multilayer sheet 2804 and M−1 adhesive laminated dielectric layers 104 are tailored (or cut) along the second cut line (3102 of FIG. 31 ) defining a third multilayer sheet 3202. The distance Da defines a width of the third multilayer sheet 3202.

As illustrated by the perspective view, with the front portions removed, 3200 b of FIG. 32B, the third multilayer sheet 3202 (of FIG. 32A) is rotated 90 degrees. A top surface 3202 a of the third multilayer sheet 3202 comprises a top surface of a plurality of rectangles of the magnetic layer 102 and dielectric layer 104 and a plurality of strips of the dielectric layer 104. A bottom surface 3202 b of the third multilayer sheet 3202 comprises a bottom surface of a plurality of rectangles of the magnetic layer 102 and dielectric layer 104 and a plurality of strips of the dielectric layer 104. In some embodiments, the plurality of rectangles of the magnetic layer 102 and dielectric layer 104 comprises at least nine rectangles respectively. In some embodiments, the plurality of strips of the dielectric layer 104 comprises at least three strips. In some embodiments, the third multilayer sheet 3202 defines the third multilayer stack 103 c.

With reference to FIGS. 33, 34, 35A-35C, and 36A-36C, cross-sectional views 3300, 3400, 3500 a, 3500 b, 3500 c, 3600 a, 3600 b, and 3600 c of various embodiments of a method for forming a magnetic field shielding structure are provided. The method is illustrated using embodiments of the memory device in FIGS. 3A-3B and 4A-4B. Notwithstanding this, the method may be used to form embodiments of the memory device in any one of FIGS. 5A-5C, 6A-6C, 7A-7C, 8A-8C, 9A-9C, 10A-10C, 11A-11C, 12A-12C, 13A-13C, 14A-14C, 15A-15C, 16A-16C, 17A-17C, 18A-18C, 19A-19C, 20A-20C, 21A-21C, 22A-22C, 23A-23C, 24A-24C, 25A-25C, and 26A-26C. Additionally, as seen hereafter, FIGS. 33, 34, 35A-35C, and 36A-36C correspond to a method for forming the magnetic field shielding structure 105 comprising the first multilayer stack 103 a, second multilayer stack 103 b, or the third multilayer stack 130 c.

Although the cross-sectional views 3300, 3400, 3500 a, 3500 b, 3500 c, 3600 a, 3600 b, and 3600 c shown in FIGS. 33, 34, 35A-35C, and 36A-36C are described with reference to a method, it will be appreciated that the structures shown in FIGS. 33, 34, 35A-35C, and 36A-36C are not limited to the method but rather may stand alone separate of the method. Although FIGS. 33, 34, 35A-35C, and 36A-36C are described as a series of acts, it will be appreciated that these acts are not limiting in that the order of the acts can be altered in other embodiments, and the methods disclosed are also applicable to other structures. In other embodiments, some acts that are illustrated and/or described may be omitted in whole or in part.

As illustrated by the cross-sectional view 3300 of FIG. 33 in the z-x plane, the chip 106 is enveloped by the insulating structure 120. A plurality of holes are defined in the insulating structure 120 outside a sidewall region of the chip 106. The electric connectors 108 extend through the plurality of holes. A top area 3302 is defined above a top surface of the chip 106. A bottom area 3306 is defined above a bottom surface of the chip 106. A first sidewall area 3304 and a second sidewall area 3308 are defined laterally offset from the sidewall region of the chip 106. A plurality of first, second, or third multilayer stack 103 a, 103 b, 103 c respectively is formed. A top multilayer stack of the plurality of first, second, or third multilayer stack 103 a, 103 b, 103 c is tailored to meet dimensions of the top surface of the chip 106 and/or insulating structure 120 and is placed in the top area 3302. A bottom multilayer stack of the plurality of first, second, or third multilayer stack 103 a, 103 b, 103 c is tailored to meet dimensions of the bottom surface of the chip 106 and/or insulating structure 120 and is placed in the bottom area 3306. A first sidewall stack of the first multilayer stack 103 a or the magnetic layer 102 is tailored to meet dimensions of a first sidewall of the chip 106 and/or insulating structure 120 and is placed in the first sidewall area 3304. A second sidewall stack of the first multilayer stack 103 a or the magnetic layer 102 is tailored to meet dimensions of a second sidewall of the chip 106 and/or insulating structure 120 and is placed in the second sidewall area 3308.

Referring to FIG. 34 , a cross-sectional view 3400 of some embodiments of the memory device of FIG. 33 in the z-y plane, in which a third sidewall area 3310 and a fourth sidewall area 3312 are defined laterally offset from the sidewall region of the chip 106. A third sidewall stack of the first multilayer stack 103 a or the magnetic layer 102 is tailored to meet dimensions of a third sidewall of the chip 106 and/or insulating structure 120 and is placed in the third sidewall area 3310. A fourth sidewall stack of the first multilayer stack 103 a or the magnetic layer 102 is tailored to meet dimensions of a fourth sidewall of the chip 106 and/or insulating structure 120 and is placed in the fourth sidewall area 3312. A stack respectively in the top area 3302, bottom area 3306, first sidewall area 3304, second sidewall area 3308, third sidewall area 3310, and fourth sidewall area 3312 is respectively attached to the respective surface of the chip 106 or insulating structure 120. In some embodiments, the first sidewall stack, second sidewall stack, third sidewall stack, and fourth sidewall stack respectively comprise a plurality of holes or openings tailored to the electric connectors 108.

As illustrated by the cross-sectional views 3500 a-3500 c of FIGS. 35A-35C in the z-x plane, the top multilayer stack, bottom multilayer stack, first sidewall stack, second sidewall stack, third sidewall stack, and fourth sidewall stack are respectively glued/attached to the top surface, bottom surface, first sidewall, second sidewall, third sidewall, and fourth sidewall of the insulating structure 120 defining the magnetic shielding structure 105.

As illustrated by the cross-sectional views 3600 a-3600 c of FIGS. 36A-36C in the z-x plane, the insulating structure 120 is formed around an outer surface of the magnetic shielding structure 105 defining a package structure 121.

With reference to FIG. 37 , a block diagram 3700 of some embodiments of a method 3700 for the method of FIGS. 27, 28A, 28B, 29, 30A, 30B, 31, 32A, and 32B is provided.

At 3702, a first magnetic foil/strip/plate is laminated with an adhesive. FIG. 27 illustrates a cross-sectional view 2700 corresponding to some embodiments of act 3702.

At 3704, a first adhesive laminated dielectric foil/strip/plate is formed over the first magnetic foil/strip/plate. FIG. 27 illustrates a cross-sectional view 2700 corresponding to some embodiments of act 3704.

At 3706, N number of pairs of adhesive laminated magnetic and dielectric foil/strip/plate are formed over the first adhesive dielectric foil/strip/plate (N is a whole number greater than or equal to 1). FIGS. 28A and 28B illustrate cross-sectional views 2800 a and 2800 b corresponding to some embodiments of act 3706.

At 3708, a second adhesive laminated magnetic foil/strip/plate is formed over the N number of pairs of adhesive laminated magnetic and dielectric foil/strip/plate defining a first multilayer stack. FIGS. 28A and 28B illustrate cross-sectional views 2800 a and 2800 b corresponding to some embodiments of act 3708.

At 3710 a, the first multilayer stack is tailored or cut to a thickness that is less than a thickness of the first multilayer stack defining a second multilayer stack. FIGS. 29, 30A, and 30B illustrate cross-sectional views 2900, 3000 a, and 3000 b corresponding to some embodiments of act 3710 a.

At 3710 b, the first multilayer stack is formed M times. FIG. 31 illustrates a cross-sectional view 3100 corresponding to some embodiments of act 3710 b.

At 3712 b, a multilayer structure is formed by gluing M−1 dielectric foils/strips/plates respectively between the M first multilayer stacks. FIG. 31 illustrates a cross-sectional view 3100 corresponding to some embodiments of act 3712 b.

At 3714 b, the multilayer structure is tailored or cut to a thickness that is less than a thickness of the multilayer structure defining the third multilayer stack. FIGS. 32A and 32B illustrate cross-sectional views 3200 a and 3200 b corresponding to some embodiments of act 3714 b.

With reference to FIG. 38 , a block diagram 3800 of some embodiments of a method 3800 for the method of FIGS. 33, 34, 35A-35C, and 36A-36C is provided.

At 3802, the first, second, or third multilayer stack is formed. FIG. 33 illustrates a cross-sectional view 3300 corresponding to some embodiments of act 3802.

At 3804 a, the first multilayer stack is tailored or cut to meet dimensions of a package top, bottom, and sidewall area. FIGS. 33 and 34 illustrate cross-sectional views 3300 and 3400 corresponding to some embodiments of act 3804 a.

At 3804 b, the second or third multilayer stack are tailored or cut to meet dimensions of a package top and bottom area. FIGS. 33 and 34 illustrate cross-sectional views 3300 and 3400 corresponding to some embodiments of act 3804 b.

At 3806 b, adhesive coated magnetic foil/strip/plate is tailored or cut to meet dimensions of the package sidewall area. FIGS. 33 and 34 illustrate cross-sectional views 3300 and 3400 corresponding to some embodiments of act 3806 b.

At 3808, tailored first, second, or third multilayer stack are attached onto the package top and bottom surfaces and tailored adhesive coated magnetic foil/strip/plate or first multilayer stack are attached onto the package sidewall surface. FIGS. 33 and 34 illustrate cross-sectional views 3300 and 3400 corresponding to some embodiments of act 3808.

Accordingly, in some embodiments, the present application relates to a magnetic field shielding structure comprising a magnetic and dielectric layer at least partially surrounding a chip.

In some embodiments, the present application provides a memory device including: a chip including a magnetoresistive random access memory (MRAM) cell; and a magnetic field shielding structure at least partially surrounding the chip and comprising a magnetic layer and a dielectric layer.

In some embodiments, the present application provides memory device including: a chip including a magnetoresistive random access memory (MRAM) cell; the chip comprises an upper face, a bottom face, and sidewalls extending between the upper face and the bottom face; a magnetic field shielding structure at least partially surrounding the chip comprising a multilayer stack; the multilayer stack is comprised of a magnetic layer and a dielectric layer; the magnetic field shielding structure comprises a top region above the upper face of the chip; a bottom region below the bottom face of the chip, and a sidewall region laterally surrounding the sidewalls of the chip; openings exists in the sidewall region of the magnetic field shielding structure; electric connectors extend through the openings and couple to the chip; a first magnetic region is located inside an inner surface of the magnetic field shielding structure and a second magnetic region is located immediately outside an outer surface of the magnetic field shielding structure; and a magnetic field in the first magnetic region is less than a magnetic field in the second magnetic region.

In some embodiments, the present application provides a method for manufacturing a memory device, the method including: forming one or more multilayer stacks, the multilayer stack comprises a magnetic layer and a dielectric layer; forming one or more magnetic layers; tailoring the one or more multilayer stacks and the one or more magnetic layers to meet dimensions of a package structure; the package structure comprises a chip including a magnetoresistive random access memory (MRAM) cell and an insulating material enveloping the chip; an outer surface of the package structure comprises the insulating material; and attaching the tailored one or more multilayer stacks and the tailored one or more magnetic layers to the outer surface of the package structure.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. 

What is claimed is:
 1. An integrated chip, comprising: a chip comprising a semiconductor device; and a shielding structure abutting the chip, wherein the shielding structure comprises a first horizontal region adjacent to a first horizontal surface of the chip, wherein the first horizontal region comprises a first multilayer structure comprising a first dielectric layer and two or more metal layers, wherein the first dielectric layer is disposed between the two or more metal layers.
 2. The integrated chip of claim 1, wherein the first dielectric layer and the two or more metal layers are vertically stacked with one another, wherein the two or more metal layers respectively have an area greater than that of the first horizontal surface of the chip.
 3. The integrated chip of claim 1, wherein the first dielectric layer is disposed laterally between the two or more metal layers, wherein bottom surfaces of the two or more metal layers are coplanar with a bottom surface of the first dielectric layer.
 4. The integrated chip of claim 3, wherein the two or more metal layers each have a width less than a width of the first horizontal surface of the chip.
 5. The integrated chip of claim 4, wherein the two or more metal layers each have a length greater than a length of the first horizontal surface of the chip.
 6. The integrated chip of claim 1, wherein the first dielectric layer has a plurality of first elongated segments intersecting a plurality of second elongated segments, wherein the two or more metal layers are spaced apart from one another by at least one individual elongated segment in the first or second elongated segments.
 7. The integrated chip of claim 1, wherein the shielding structure comprises a second horizontal region adjacent to a second horizontal surface of the chip opposite the first horizontal surface, wherein the second horizontal region comprises a second multilayer structure comprising a second dielectric layer and two or more other metal layers.
 8. The integrated chip of claim 7, wherein the shielding structure comprises a vertical structure disposed on opposite sides of a first pair of opposing sidewalls of the chip, wherein the vertical structure extends continuously between the first and second multilayer structures.
 9. The integrated chip of claim 8, wherein the vertical structure comprises a third multilayer structure configured as the first multilayer structure or the second multilayer structure.
 10. The integrated chip of claim 8, wherein the vertical structure is disposed on opposite sides of a second pair of opposing sidewalls of the chip, wherein the second pair of opposing sidewalls continuously extend between the first pair of opposing sidewalls.
 11. An integrated chip, comprising: a semiconductor structure having a first lateral surface opposite a second lateral surface and a pair of sidewalls extending between the first and second lateral surfaces; and a housing structure comprising a first lateral region, a second lateral region, and a sidewall region extending between the first and second lateral regions, wherein the semiconductor structure is spaced vertically between the first and second lateral regions, and wherein the housing structure comprises a shielding stack comprising a plurality of metal structures and an insulating structure spacing the metal structures from one another.
 12. The integrated chip of claim 11, wherein the semiconductor structure comprises a memory cell.
 13. The integrated chip of claim 11, wherein the first and second lateral regions respectively comprise the shielding stack, wherein in top view an area of the shielding stack is greater than areas of the first and second lateral surfaces.
 14. The integrated chip of claim 13, wherein the sidewall region comprises a support structure extending vertically from the first lateral region to the second lateral region.
 15. The integrated chip of claim 13, wherein the sidewall region comprises the shielding stack.
 16. The integrated chip of claim 11, wherein the sidewall region comprise openings vertically aligned with the pair of sidewalls of the semiconductor structure, wherein conductive wires extend from outside the housing structure through the openings towards the pair of sidewalls of the semiconductor structure, wherein the conductive wires are electrically coupled to the semiconductor structure.
 17. A method for forming an integrated chip, comprising: forming a first multilayer structure comprising a first metal layer and a first dielectric layer; trimming the first multilayer structure to meet dimensions of a first outer surface of a package structure, wherein the package structure comprises a chip; and attaching the first multilayer structure to the first outer surface of the package structure.
 18. The method of claim 17, further comprising: forming a second multilayer structure comprising a second metal layer and a second dielectric layer; trimming the second multilayer structure to meet dimensions of a second outer surface of the package structure; and attaching the second multilayer structure to the second outer surface of the package structure.
 19. The method of claim 17, wherein the first multilayer structure comprises a second metal layer disposed on the first dielectric layer.
 20. The method of claim 19, wherein an adhesive material is disposed between the first dielectric layer and the first and second metal layers. 